Many of today's non-volatile semiconductor integrated circuit chips have one or more pins designed to receive voltages higher than their device breakdown voltages from external sources. Most of these externally supplied high voltages are around 12V that are higher than today's device breakdown voltage of 10V. For reliability concern, the circuitry and devices that receive the higher voltages must be specially handled to prevent the input devices from breakdown caused by the higher voltage stress on either a junction or gate. Therefore, higher voltage breakdown-free input circuitry is a very important feature for semiconductor integrated circuit chips. The higher voltage, generally referred to as VPP, is defined as an external voltage level higher than the power supply voltage VDD and the breakdown voltage of the devices of the chip. The higher voltage is usually provided by an external source such as a programmer device or, if available, from the system where the chip is mounted.
High voltage input circuitry has been widely used in many different applications. However, allowing an input voltage higher than the breakdown voltage of a device is always a concern to the device's reliability. One common practice is to limit the device life cycles and operating hours. A popular use of a high voltage input is for the purpose of forcing an integrated circuit chip to enter special test modes. A high voltage detector is normally built in the chip. By applying a high voltage to the high voltage input pin(s), the detector detects the high voltage and sends a signal to a state machine which allows the chip to enter the pre-designed modes.
Therefore, the design and process engineers can use this feature to access the test modes for debugging or engineering characterization. In addition, the application engineers can use this feature to access their specified test modes for production test. Because the chip receives only low voltage inputs, i.e. Vdd, during its normal operation, this feature effectively prevents customers or other unauthorized persons from accidentally entering the test modes that trigger undesired operations of the chip as well as the system.
Another common application of the high voltage input is in the field of electrically-programmable non-volatile memories. Almost all electrically-programmable non-volatile memories, including EPROM, EEPROM and Flash memory, require high voltages to erase data from or write data to the memory cells. For example, an EPROM (Electrically Programmable Read Only Memory) requires applying approximately 12 to 13 volts to the gate, and 5 to 6 volts to the drain of the memory cell transistor to program a `1` data into the cell.
Due to the requirement of high voltage sources, the process of programming memory data is typically done in a manufacturer's facility. Before the chip is shipped to customers, the old data (if there is any) of the entire memory are erased at one time by exposing the chip under UV light through a crystal window on the package. Then, the new data of the entire memory are programmed by an external device. During this operation, an external programmer device supplies the required high voltages and timing control signals.
Unlike EPROM, the mechanism of memory erasure in the later developed EEPROM and flash memories is significant improved. Both EEPROM and flash memories can be erased electrically without being exposed under UV light, thus eliminating the crystal window required for UV exposure. Manufacturing and reprogramming cost is greatly reduced. However, both memories require high voltages to erase memory data electrically.
There are various EEPROM and flash memory technologies in the market today. Technologies for flash memories are widely researched and developed. Most of them target applications that have different erasing or programming requirements and schemes. The details for the operation of EEPROM and flash memory are known to persons skilled in the art and will not be discussed here. In essence, most of the erasing operations of existing EEPROM and flash memories are based on same fundamentals that require a high voltage to be applied to one or more of the cell transistor's electrical poles. Compared with the high voltage detector circuit used for entering test modes only, the high voltage input circuit for non-volatile memories has more demanding input specifications. It generally requires higher current driving capability for providing the internal memory cells with sufficient current to erase and program the memory cells.
As the fabrication process of non-volatile memories continue to migrate towards the reduction of device oxide thickness and junction depth for speed enhancement reason, the high voltage input circuitry design has become an important and tough challenge. The junction depth and well spacing of these devices also continue to shrink for more compact layout and higher integration. These technologies result in lower breakdown voltage in the high voltage input circuitry of a device. The lower breakdown voltage can no longer withstand voltages as high as 12 to 13 volts that are provided by external voltage sources conventionally.
To cope with the lower breakdown voltage in the newer device, the industry has to replace the existing programmers as well as the systems so that a relatively lower high voltage can be provided. However, the high replacement cost usually forces the manufacturer of a device chip to keep two technologies at the same time, i.e., using the old technology for the high voltage input circuit that requires thicker gate oxide and deeper junction depth while using the newer technology for the rest of the low-voltage device. Therefore, it would be very advantageous for the industry if the newer devices could be made capable of receiving voltages higher than their breakdown voltage as used in the conventional technology.
As shown in FIGS. 1 and 2, two types of high voltage input circuits have been disclosed in U.S. Pat. No. 5,420,798. The circuit shown in FIG. 1 uses a PMOS (P1) for receiving and passing a high voltage VPP. The gate of the PMOS is connected to VDD. When the high voltage input is not applied, typically the input pin is connected to VDD. This turns off the PMOS and the output of the inverter is at a high state indicating a normal mode.
When the high voltage input VPP is applied to the input pin, the PMOS is turned on because the high voltage is greater than the sum of VDD and the threshold voltage VTP of the PMOS. The voltage at the input node of the inverter is determined by the pull-up resistor R1, the PMOS turn-on resistance, and the pull-down resistor R2. By properly selecting these resistors, the input node is set to a relatively high level that causes the output of the inverter to be low. Consequently, the device chip is put into a specified test mode by the low output signal.
FIG. 2 shows another high voltage input circuitry. The basic structure of the PMOS as well as the resistors R1 and R2 as shown in FIGS. 1 and 2 are identical. One or more NMOS (N1) each having its gate and drain connected to form a diode are added between the resister R1 and the PMOS in series. As the high voltage passes each diode, it drops approximately a threshold voltage VTN of an NMOS. Therefore, these NMOS diodes in series reduce the voltage applied to the source of the PMOS, thus reducing the stress of the PMOS and preventing it from breakdown. In addition to these two circuits, there are also other prior arts for the high voltage input circuits. However, almost all the prior arts have very similar concept as these two. Examples can be found in U.S. Pat. Nos. 5,420,798 and 5,493,244.
Comparing the two prior art circuits of FIGS. 1 and 2, the one shown in FIG. 1 is less preferred because it has a significant drawback that the high voltage pin must be dedicated to the high voltage input only. That is due to the fact that the circuit uses a PMOS to receive the high voltage input, thus the N-well of the PMOS must be also connected to the same high voltage input pin in order to avoid a P-N junction forward current. When a high voltage is not applied, the voltage at the input pin is typically VDD. Dedicating one pin simply to the test mode is not economical.
Moreover, for many applications that require multiple high voltage input pins, the pin count dramatically increases. It is highly desirable that the high voltage input pins be used as other low voltage pins such as address input pins when they are not applied with a high voltage. However, because the N-well of the PMOS is directly connected to a high voltage input pin, using this pin as a normal input pin or output pin causes the N-well to be switched between VDD and ground. It may raise a serious latch-up concern. As a result, the prior art shown in FIG. 1 is not very practical.
On the other hand, the prior art shown in FIG. 2 does not have such a latch-up concern because no well is directly connected to the high voltage input pin. Thus, the high voltage input pin can be used for other signals. However, there are cases that a significant breakdown problem of the high voltage input circuit may occur to this circuitry. Considering the circuit shown in FIG. 2, when applied with a high voltage, the maximum high voltage stress is put on the drain junction of the NMOS diode (N1) instead of the PMOS (P1). Because the NMOS is located on the P-substrate that is always connected to ground, the drain junction experiences VPP to ground voltage difference which may cause junction and gate-oxide breakdown to occur if VPP is exceeding the allowed breakdown voltages.
Although the original idea of adding the NMOS diode is to protect the PMOS from breakdown, unfortunately it does not protect the NMOS diode itself. All known prior arts do not seem to handle this junction and gate-oxide breakdown problems with care. The NMOS is simply disposed in the P-substrate without any protection. As a result, the breakdown of the NMOS becomes a killing factor for the high voltage input circuitry.